Sahaaya has extensive experience in complete ASIC development process and have successfully taped out several ASICs in advanced silicon node.

Architecture Specification:

• Full chip and/or system Architecture specification development
• Block and sub-system Micro-Architecture specification development.
• Developing Architecture Models (C/C++, System-C, MATLAB).
• Prototyping algorithms and architectural concepts on FPGA platform.
• Converting Architectural models to High-Level-Synthesis code.
• 3rd party IP specification review.
• Power, Area and Performance Analysis.

Logic Design | Low-Power Design Implementation:

• RTL Logic Design: Verilog, System-Verilog
• Automated Register Generation: SemiForce CSR-Reg
• IP integration flow: IP-XACT, EMACS Auto-Verilog mode
• Synthesis: Design Compiler, Physical Compiler, Fusion Compiler, Genus.
• Timing Analysis: PrimeTime. Tempus.
• Lint / Clock-Domain-Crossing (CDC) / Formal Verification: Spyglass.
• Low Power design: Power-Compiler, UPF flow.
• Design-For-Testability (DFT): TestMax DFT, DFT Advisor.

Design Verification and Emulation:

• Block, Sub-system and Full Chip verification: System-Verilog UVM, C/C++
• Simulation and Debug: VCS, Verdi, Modelsim, Questa, Incisive.
• Directed, Pseudo-Random and Gate Level Verification.
• Comprehensive coverage analysis and Assertion generation.
• Emulation: Palladium, Zebu, Veloce, FPGA.
• Post-Silicon Bring Up

Back-End Physical Implementation:

Sahaaya works closely with our partners for ASIC Backend implementation from netlist to GDSII. We take on the Engineering and Project Management responsibilities to execute Floor-planning, Placement and Routing, Clock Tree Insertion, DFT, post-layout Timing Closure, DRC/LVS and GDS database generation. We also manage relations with foundry and packing vendors.